I intend to verify the design this time around, before laying out the PCBs, by building the complete computer on bread board. I basically have the whole thing designed on paper and it's now just a matter of building it. OK, better late than never here is where I currently am at, construction wise, with the Model 1 TRS-80 clone. I'll divide my 16 MHz by 9 for 1.778 MHz, which is more than close enough. The CPU clock in the original TRS-80 was 1.774 MHz (10.6445 MHz divided by 6). The master clock source will be a generic 16 MHz oscillator. Maybe RS just had a preexisting stockpile of 10.6445 MHz crystals to use up? To mitigate these issues and to avoid having to source a 10.6445 MHz crystal, in my clone design I've lowered the pixel-shifting clock frequency to 8MHz. Also 10.6445 MHz is pushing the video bandwidth limitation of your typical TV-based display monitor a bit too far and it was a complaint back in the day that the high-resolution video characters were ill-defined and blurry on the screen. Unless displayed on a TV/monitor having a tweakable (expandable) width control for the horizontal picture size, that will result in a fairly squished up display horizontally. That high frequency meant that all 384 pixels of a complete row were serially shifted out in just 36uS of the complete 63.13uS line period. Perhaps that was a commonly available crystal 40 years ago, but you certainly can't buy a 10.6445 MHz crystal off the shelf today. Did you get as far as of yet as testing any or all of your VDHL on an FPGA development kit or the like? There were some weird design decisions made with the original TRS-80 for example the odd-ball 10.6445 MHz pixel-shifting clock frequency. Maybe I should just make provision for an external '1771 emulator to be plugged in? Hm, I will see.